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HCF40174B
HEX "D" TYPE FLIP-FLOP
s
s
s s
s s
STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40174BEY HCF40174BM1 T&R HCF40174M013TR
DESCRIPTION HCF40174B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40174B consists of six identical "D" Type flip-flops having independent DATA inputs. The
CLOCK and CLEAR inputs are common in all six units. Data is transferred to the Q outputs on the positive-going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input.
PIN CONNECTION
September 2002
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HCF40174B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 3, 4, 6, 11, 13, 14 2, 5, 7, 10, 12, 15 9 1 8 16 SYMBOL D1 to D6 Q1 to Q6 CLOCK CLEAR VSS VDD NAME AND FUNCTION Data Inputs Data Outputs Common Clock Inputs Common Clear Inputs Negative Supply Voltage Positive Supply Voltage
TRUTH TABLE
INPUTS CLOCK DATA L H X X
X : Don't Care NC : NO CHANGE
OUTPUT CLEAR H H H L Q L H NC L
X
FUNCTIONAL DIAGRAM
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HCF40174B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF40174B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.02 0.02 0.02 0.02 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.1 -2.6 -0.31 -0.75 -0.68 -1.6 -2.3 -5.4 0.44 1 1.1 2.6 3.0 6.8 10-5 5 -0.9 -0.25 -0.54 -1.84 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -0.9 -0.25 -0.54 -1.84 0.36 0.9 2.4 Max. 1 2 4 20 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 30 60 120 600 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 150 70 50 100 50 40 100 50 40 20 10 0 40 20 15 65 30 20 50 25 20 Max. 300 140 100 200 100 80 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time : Clock to Output tPHL Propagation Delay Time : Clear to Output
ns
tTHL, tTLH Transition Time
ns
tsetup
Data Setup Time
thold
Data Hold Time
tW
Clock Input Pulse Widht Low Level Clear Input Pulse Widht HIGH and LOW Clock Input Rise or Fall Time Clear Removal Time
tW
40 20 10 80 40 30 130 60 40 100 50 40
ns
ns
ns
ns 15 15 15
tr, tf
s
trem
fCL
Maximum Clock Input Frequency
0 0 0 3.5 6 8
-40 -15 -10 7 12 16
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF40174B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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HCF40174B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF40174B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF40174B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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